Types of Computer Architecture

computer architecture

There are many types of computer architecture. You've probably heard of RISC architecture and Harvard architecture. But what are they? And how do you tell which one is right for you? Let's explore these types of architecture in this article. Here's a quick overview. You'll also learn about Von Neumann, RISC, and Harvard architecture. These are all important considerations when choosing a processor. Read on to learn more!

Instruction set architecture

An instruction set architecture (ISA) defines how a processor functions. Before, architectures were separate from compilers, but that has changed. Compilers now depend on the ISA to make the most efficient use of the hardware available to them. The ISA should be friendly to the compiler, as it can provide important information about the regularity, orthogonality, and weighing of options. This article describes how ISAs affect computer design.

Von Neumann architecture

The basic components of the Von Neumann computer architecture include a single ALU, a memory, and a bus connecting the first two. The memory stores words, each of 16 bits, and is transferred between the CPU and memory over two clock cycles. One clock cycle is used to transfer the data, and the second is used to transmit the address. This same mechanism is also used to transfer information from the CPU to memory. Hence, the Von Neumann architecture is referred to as a logical architecture.

Harvard architecture

A Harvard architecture is one type of computer memory hierarchy. In contrast to the von Neumann model, which provides a single address space for a computer's memory, Harvard architecture has a memory hierarchy, with the instructions and data coming from the CPU's data cache and instruction cache respectively. For most programmers, this type of architecture is not a necessity, but for those who need to store instructions in the memory, it is a valuable knowledge to have.

RISC architecture

RISC computer architecture starts with a small set of commonly used instructions. Increasing the number of instructions in a pipeline can increase the complexity of the CPU and slow its processing speed by as much as 10%. As the number of pipeline stages increases, so does the complexity of the instruction set. In addition, RISC architecture is not well-suited for processing large amounts of data. Typically, data in a cache is not accessed immediately from memory, but must route through the cache to reach the register file.

Common control lines in processors

While different processors have a range of control lines, there are some that are common across all types of devices. The control bus contains output signals and valid addresses. Input control lines usually include the clock input, reset, and interrupt. The processor will use this data to perform operations. In some cases, the processor may have separate units for multiplication and bit shifting. In the event of an interrupt, the processor will load the next vector into the program counter. The processor will then execute the service routine associated with the interrupt.

Bus interface in processors

The bus interface is a unit in the processor that interacts with the rest of the PC. It is responsible for moving information over the processor's data bus, the primary means of transferring information in a computer. It responds to processor signals and also generates and receives signals from other parts of the system. A processor has a memory unit that contains one or more N-bit memory addresses. These addresses are used to identify individual locations within the memory.


ISAs are a form of computer architecture that isolates software from hardware. They allow hardware designers to focus on the hardware and worry less about how software is developed on top of the ISA layer. Hardware and software designers can then work together without concern over the details. While ISAs are widely used, there are some differences among them. Listed below are some of the differences and benefits of ISAs. They can be helpful in identifying hardware and software compatibility issues.


The DMAC computer architecture uses a device manager and a data bus to transfer data between devices. When the device needs to transfer data, it sends a DMA request signal to the DMA controller, which acknowledges it and requests a bus grant signal. The DMAC can handle up to n external devices and is capable of transferring data in one of three modes: burst, buffer, and direct mode. A DMA controller has three registers: an address register that specifies where in memory the data should be transferred, a word count register, and a DMA register.

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